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Firmware development engineer with a focus in low-level design and implementation. I am…
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Here's an interesting Tuesday morning tidbit for you! 🌊 Blue Wave's Nuclear-Grade AI ™️ applications are helping to keep energy prices down. Get…
Here's an interesting Tuesday morning tidbit for you! 🌊 Blue Wave's Nuclear-Grade AI ™️ applications are helping to keep energy prices down. Get…
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Advances in Nuclear Fuel Management (ANFM) got off to a great start! Blue Wave hosted the first panel of the conference discussing the industry’s…
Advances in Nuclear Fuel Management (ANFM) got off to a great start! Blue Wave hosted the first panel of the conference discussing the industry’s…
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Sometimes, the right opportunities find you at just the right moment. That’s exactly what happened when I reconnected with Zach Greenberger. As I…
Sometimes, the right opportunities find you at just the right moment. That’s exactly what happened when I reconnected with Zach Greenberger. As I…
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To accelerate the deployment of edge AI, we need to address developers’ challenges by providing them with the right hardware and software for their…
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👏 STMicroelectronics was honored to mark its longstanding NYSE, listing and commitment to all our stakeholders in the US during the September 5…
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Heading to Purdue University next week during #IR #IndustrialRoundtable to find another generation of semiconductor innovators to work at Micron…
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Tutti i “residenti” per così dire, temporanei o permanenti che fossero, nei siti di #STMicroelectronics in Italia hanno avuto l’opportunità a giugno…
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Chad Wallace
What if switching noise from DC-DC converters is coupled onto high-speed signal lines—and quietly degrades signal integrity? I just wrapped up DesignCon (high-speed links) and I’m heading to APEC (power electronics) in a few weeks as my final conference stop. It’s been making me think about what happens as systems get more tightly integrated: 💠 Power electronics and signal integrity are often treated as separate worlds—each with its own toolchains, complexity, and specialists. 💠 However, Integration forces them back together: power wants low IR drop and short return paths, while signals want minimal distance, controlled impedance, and high edge rates—so they end up in close proximity. Chip to chip and rack to rack communication is trending toward PAM4 (4 analog levels per "channel") to increase the data rate. However, this reduces BER margin, making the signal lines much more sensitive to external noise sources, including the noise from the switching converters and the high-frequency load pull transients of the chip itself. So the question I keep thinking about is: 💠 How do we detect these power and signal interactions earlier in the design flow? 💠 Are we slowly designing ourselves into systems with too many interactions to handle properly? That’s essentially what the industry means by “shift left”—catching coupling paths, PDN resonances, and layout-driven issues before they become late-stage surprises. If you’ve dealt with this (PDN-induced jitter, ground bounce, supply ripple folding into receivers, via/return-path headaches, etc.), I’d love to hear what you’ve seen—and what actually helped. Also: I’ll be releasing a primer next week on the fundamentals of buck converters, aimed at building an intuitive, realistic sense of the design tradeoffs behind modern DC-DCs.
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