Benito R. Fernández, PhD, Visionary, Founder, CTO

A system and a method of determining the persistent presence of an authorized user while performing allowed operations on an allowed resource of the system while satisfying certain context-sensitive restrictions are disclosed. The system receives a request from a user to authenticate him/her. The system authenticates the user using biometric information of the user or any other authentication mechanism in a given context-sensitive restriction. If the user is authenticated, then the system… Show more

A system and a method of determining the persistent presence of an authorized user while performing allowed operations on an allowed resource of the system while satisfying certain context-sensitive restrictions are disclosed. The system receives a request from a user to authenticate him/her. The system authenticates the user using biometric information of the user or any other authentication mechanism in a given context-sensitive restriction. If the user is authenticated, then the system allows the user to perform the allowed operation using the allowed resources in the context-sensitive restriction. If the authentication fails to indicate that the user is an unauthorized user, then the system initiates a resolution process to halt or terminate the allowed operation to restrict or obfuscate the allowed operation from being accessed by the unauthorized user. In one embodiment, the system comprises an External Companion Device (ECD) paired with the system to perform the authentication and manage the allowed operations on the resources of the system under the context-sensitive restriction. Show less

Described herein is a combination of mixed-signal hardware and software that is capable or realizing hybrid chaotic oscillators that can be tuned digitally. This includes the type/class of chaotic oscillator, initial conditions, nonlinear elements, thresholds, nonlinear event surfaces, delays, etc. At the same time, tunable methods of how to use the chaotic oscillator information to encrypt and decrypt both analog and digital information is presented. This will make the secure information not… Show more

Described herein is a combination of mixed-signal hardware and software that is capable or realizing hybrid chaotic oscillators that can be tuned digitally. This includes the type/class of chaotic oscillator, initial conditions, nonlinear elements, thresholds, nonlinear event surfaces, delays, etc. At the same time, tunable methods of how to use the chaotic oscillator information to encrypt and decrypt both analog and digital information is presented. This will make the secure information not vulnerable by digital information compromises or hardware breach. Show less

A method to tune electronic devices in general using R/2R ladder networks to obtain fixed or variable accurate properties that may include, but are not limited to resistance, current, voltage, and/or timing. As a particular application, a method for internally calibrating a digital-to-analog converter is shown in detail. The DAC uses an extended R/2R ladder to improve the converting accuracy by mapping the extended bits into the original bits. A mapping matrix is maintained, which can be… Show more

A method to tune electronic devices in general using R/2R ladder networks to obtain fixed or variable accurate properties that may include, but are not limited to resistance, current, voltage, and/or timing. As a particular application, a method for internally calibrating a digital-to-analog converter is shown in detail. The DAC uses an extended R/2R ladder to improve the converting accuracy by mapping the extended bits into the original bits. A mapping matrix is maintained, which can be rewritten by an internal calibration process. Show less

Abstract:
An apparatus for solving time-continuous differential equations is disclosed. The apparatus includes a group of hybrid integrators interconnected to each other. Each one of the hybrid integrators includes an analog integrator, a conversion logic and multiple digital registers. The analog integrator generates an analog output, and the conversion logic along with the digital registers converts the analog output to a digital output. The analog output and the digital output are then… Show more

Abstract:
An apparatus for solving time-continuous differential equations is disclosed. The apparatus includes a group of hybrid integrators interconnected to each other. Each one of the hybrid integrators includes an analog integrator, a conversion logic and multiple digital registers. The analog integrator generates an analog output, and the conversion logic along with the digital registers converts the analog output to a digital output. The analog output and the digital output are then combined to yield an integrated output. The integrated output is fed to the hybrid integrators within the group. Show less

Abstract:
A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, F.sub.x, F.sub.y, F.sub.xx, F.sub.xy, F.sub.yy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital… Show more

Abstract:
A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, F.sub.x, F.sub.y, F.sub.xx, F.sub.xy, F.sub.yy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor .phi.(x.sub.0,y.sub.0) of the Taylor series equation. The DAC control register uploads a lead term F(x.sub.0,y.sub.0) of the Taylor series equation from the digital processor to the DAC. The first-order digital registers controls resistances of the R2R ladders. The second-order digital registers uploads coefficients F.sub.x, F.sub.y, F.sub.xx, F.sub.xy, F.sub.yy of the Taylor series equation from the digital processor to the DAC. The analog integrator adds outputs from the DAC and the R2R ladder to generate approximation results for the Taylor series equation. Show less

Abstract: The present invention is a fully connected feed forward network that includes at least one hidden layer 16. The hidden layer 16 includes nodes 20 in which the output of the node is fed back to that node as an input with a unit delay produced by a delay device 24 occurring in the feedback path 22 (local feedback). Each node within each layer also receives a delayed output (crosstalk) produced by a delay unit 36 from all the other nodes within the same layer 16. The node performs a… Show more

Abstract: The present invention is a fully connected feed forward network that includes at least one hidden layer 16. The hidden layer 16 includes nodes 20 in which the output of the node is fed back to that node as an input with a unit delay produced by a delay device 24 occurring in the feedback path 22 (local feedback). Each node within each layer also receives a delayed output (crosstalk) produced by a delay unit 36 from all the other nodes within the same layer 16. The node performs a transfer function operation based on the inputs from the previous layer and the delayed outputs. The network can be implemented as analog or digital or within a general purpose processor. Two teaching methods can be used: (1) back propagation of weight calculation that includes the local feedback and the crosstalk or (2) more preferably a feed forward gradient decent which immediately follows the output computations and which also includes the local feedback and the crosstalk. Show less